RTL Design Engineer - Senior (US)
Company: Lancesoft Inc
Location: Santa Clara
Posted on: April 23, 2024
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Job Description:
Location: Onsite San Jose, CAJOB DUTIES: Responsible for RTL
design using Verilog HDL for implementation and debug. Read and
comprehend System on Chip level architectural specification. Write
microarchitecture specification for new and modified functions.
Responsible for linting and simulation of design. Work with
synthesis and backend teams for physical implementation. EDUCATION:
Bachelor's or Master's in Computer EngineeringKEY RESPONSIBILITIES:
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components. Guarantee
quality/timely deliverables meeting projects schedule. Help to
improve/automate design process.PREFERRED EXPERIENCE: Knowledge of
RISK-V processor integration Express Multi-clock domain designs.
Design constraints for synthesis and static timing analysis.
Knowledge of AXI/AMBA protocol Knowledge of front-end RTL design
tools and methodologies. Knowledge of scripting languageslikePerl,
tcl or cshellby Jobble
Keywords: Lancesoft Inc, San Bruno , RTL Design Engineer - Senior (US), Engineering , Santa Clara, California
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