ASIC Design Verification Engineer, University Graduate
Company: Google
Location: Cupertino
Posted on: January 12, 2026
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Job Description:
Minimum qualifications: Bachelors degree in Electrical
Engineering, Computer Engineering, Computer Science, a related
field, or equivalent practical experience. Experience with
SystemVerilog (i.e. SystemVerilog Assertions or functional
coverage). Preferred qualifications: Masters degree or PhD in
Electrical Engineering, Computer Engineering or Computer Science,
with an emphasis on computer architecture. Experience in verifying
digital logic at RTL using SystemVerilog for ASICs. Experience in
power aware verification, gate level simulations, and post silicon
bring-up. Experience with the full verification life cycle.
Familiarity with ASIC standard interfaces. About the job In this
role, you’ll work to shape the future of AI/ML hardware
acceleration. You will have an opportunity to drive cutting-edge
TPU (Tensor Processing Unit) technology that powers Googles most
demanding AI/ML applications. You’ll be part of a team that pushes
boundaries, developing custom silicon solutions that power the
future of Googles TPU. Youll contribute to the innovation behind
products loved by millions worldwide, and leverage your design and
verification expertise to verify complex digital designs, with a
specific focus on TPU architecture and its integration within
AI/ML-driven systems. In this role, you will use your design and
verification exposure to verify complex digital designs. You will
collaborate closely with design and verification engineers in
active projects and perform verification. Using your SystemVerilog
coding and problem solving skills, you will build efficient and
effective constrained-random verification environments that
exercise designs through their corner-cases and expose all types of
bugs. You will be responsible for the full life cycle of
verification, from verification planning to test execution, to
collecting and closing coverage. The AI and Infrastructure team is
redefining what’s possible. We empower Google customers with
breakthrough capabilities and insights by delivering AI and
Infrastructure at unparalleled scale, efficiency, reliability and
velocity. Our customers include Googlers, Google Cloud customers,
and billions of Google users worldwide. Were the driving force
behind Googles groundbreaking innovations, empowering the
development of our cutting-edge AI models, delivering unparalleled
computing power to global services, and providing the essential
platforms that enable developers to build the future. From software
to hardware our teams are shaping the future of world-leading
hyperscale computing, with key teams working on the development of
our TPUs, Vertex AI for Google Cloud, Google Global Networking,
Data Center operations, systems research, and much more. The US
base salary range for this full-time position is $113,000-$161,000
bonus equity benefits. Our salary ranges are determined by role,
level, and location. Within the range, individual pay is determined
by work location and additional factors, including job-related
skills, experience, and relevant education or training. Your
recruiter can share more about the specific salary range for your
preferred location during the hiring process. Please note that the
compensation details listed in US role postings reflect the base
salary only, and do not include bonus, equity, or benefits. Learn
more about benefits at Google . Responsibilities Plan the
verification of complex digital design blocks by fully
understanding the design specification and interacting with design
engineers to identify important verification scenarios. Create and
enhance constrained-random verification environments using
SystemVerilog and UVM, or formally verify designs with SVA and
industry leading formal tools. Identify and write all types of
coverage measures for stimulus and corner-cases. Debug tests with
design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show
progress towards tape-out.
Keywords: Google, San Bruno , ASIC Design Verification Engineer, University Graduate, Education / Teaching , Cupertino, California
